QuickLogic Corporation (NASDAQ:QUIK) Q4 2025 Earnings Call Transcript

QuickLogic Corporation (NASDAQ:QUIK) Q4 2025 Earnings Call Transcript March 3, 2026

QuickLogic Corporation misses on earnings expectations. Reported EPS is $-0.17 EPS, expectations were $-0.11.

Operator: Ladies and gentlemen, good afternoon. At this time, I would like to welcome everybody to QuickLogic Corporation’s Fourth Quarter and Fiscal 2025 Earnings Results Conference Call. As a reminder, today’s call is being recorded. I would now like to turn the conference over to Ms. Alison Ziegler of Darrow Associates. Ms. Ziegler, please go ahead.

Alison Ziegler: Thank you, operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer; and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our future profitability and cash flows, expectations regarding our future business and expected revenue growth and statements regarding the timing, milestones and payments related to our government contracts. Actual results may differ due to a variety of factors, including delays in the market acceptance of company’s new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers’ products, the risk that new orders may not result in future revenues, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low power, competitive pricing and short time to market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters and other business interruptions that could disrupt supply or delivery of or demand for the company’s products and changes in tax rates and exposure to additional tax liabilities.

For more detailed discussions of the risks, uncertainties and assumptions that could result in those differences, please refer to the risk factors discussed in QuickLogic’s most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information, which speak as of the respective dates of any new information or future events. In today’s call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR web page that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate X account, Facebook page and LinkedIn page as channels of distribution of information about its business.

Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today’s call will be posted on QuickLogic’s IR web page shortly after the conclusion of today’s earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

Brian C. Faith: Thank you, Alison. Good afternoon, everyone, and thank you all for joining our fourth quarter 2025 conference call. While certain contract delays over the course of the year resulted in much lower-than-expected 2025 revenue, we accomplished numerous tangible milestones that set the stage well for 2026 and beyond. Underscoring this is our forecast for nearly 50% sequential revenue growth in Q1, large contracts for very high-density eFPGA Hard IP cores that are in late stages of negotiation and the acceleration of our storefront business model, which we believe will drive a meaningful revenue contribution beginning in 2026. I’ll take a few minutes now to update you on these and other accomplishments. In our February 18 press release, we announced QuickLogic was awarded a $13 million tranche for our ongoing contract with the U.S. government that was initiated in 2022.

We will begin recognizing revenue from this tranche in Q1. In line with my comments during our last earnings conference call, this tranche funds increased quarterly revenue recognition relative to 2025. In parallel with our U.S. government contract, QuickLogic internally funded the development of an SRH FPGA test chip. Last August, we delivered design files to GlobalFoundries to fabricate our SRH FPGA test chip using its 12LP process. This chip was designed to meet the specific requirements of certain large DIBs that have programs in development today that are good candidates for this device. This investment positions us very well as the only source available today for a U.S. fabricated FPGA that addresses the full spectrum of radiation hardness requirements.

We received our SRH FPGA test chip samples earlier in Q1 and announced in a January 14 press release that we have received orders for our SRH FPGA dev kit that enables DIBs to evaluate the test chips. I view this as a strong demand signal and our first tangible step towards what I believe will be hundreds of millions of dollars in potential storefront business for our discrete SRH FPGA during the coming years. Beyond the discrete SRH FPGA market, we are leveraging this test chip to cast a much broader net. In addition to the applications that require strategic radiation hardness that are most likely to design using our storefront discrete SRH FPGA, there are many other applications with less rigorous radiation requirements that may prefer to integrate our SRH eFPGA Hard IP in ASICs. DIBs are already using GlobalFoundries’ 12LP fabrication process for various levels of radiation hardness in ASIC designs.

By demonstrating our SRH FPGA test chip that is also fabricated on 12LP, we are positioning QuickLogic to address both discrete SRH FPGA requirements as well as provide DIBs with the confidence they need to integrate our SRH eFPGA Hard IP in future ASIC designs. In some cases, these DIBs may also elect to utilize our storefront services for their ASIC designs. The short story here is by leveraging the milestones accomplished in 2025, we believe we are very well positioned to successfully address both discrete and embedded FPGA designs across the full spectrum of radiation hardness requirements. And with the architectural enhancements we implemented last year that are extensible to 12LP, we have significantly expanded our SAM in these markets to include the lucrative applications for very high-density discrete and embedded FPGA.

During our last conference call, I stated that a mid-7-figure eFPGA Hard IP contract leveraging Intel 18A was pushed into 2026 due to a delay in government funding. Based on our conversations with this DIB, we remain highly confident we will be awarded this contract once it is funded. While the timing of funding remains uncertain, our discussions with this DIB have expanded to include the potential of QuickLogic providing storefront services for the customer-designed ASIC that will include our eFPGA Hard IP. We expect that we will learn more about the potential expansion to storefront and the timing for this award in the coming months. During this funding delay and the discussions about expanding the scope of our participation, we have worked closely with this DIB on a variety of projects.

Through these efforts, we have been awarded 3 smaller Intel 18A contracts that total well over $1 million, and a fourth is pending that will bring the total to nearly $2 million. The first 2 contracts were for Intel 18A test chips. We delivered IP for both in 2025 and expect to receive an allotment of test chips for our internal evaluation next quarter. The third contract was for a 1 million LUT feasibility study that we completed in Q4. A fourth contract, which we anticipate being awarded yet this quarter, leverages the architectural enhancements developed during the 1 million LUT study. In support of this contract, we will deliver Hard IP for a very large Intel 18A eFPGA core, the customer plans to integrate into its ASIC that is targeted for tape-out during the second half of 2026.

The architectural enhancements we developed in support of the 1 million LUT study can be leveraged across all advanced fabrication nodes, which we define as 12 nanometers and smaller. These enhancements reduce power consumption, increase performance and reduce the silicon area required for a given size block of our core FPGA technology. In industry terms, the enhancements materially improve our PPA. With these architectural enhancements in place, we can address the lucrative markets that require very high-density eFPGA cores in ASIC designs and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA Hard IP and discrete devices, including our SRH FPGA, chiplets and other storefront opportunities. In addition to these DIB contracts, we are working closely with a large commercial customer on a new Intel 18A contract valued at several million dollars.

We originally expected this contract would be awarded in late Q4. However, the customer decided to expand the size of the eFPGA core in their ASIC to provide greater programmable flexibility. While this is a beneficial trend for QuickLogic, it has delayed the contract award. We are currently forecasting this contract will be awarded during Q2. During our November 2025 conference call, I stated that we would soon announce the expansion of our involvement with a DIB that specializes in cybersecurity for strategic and tactical weapon systems. On December 8, we issued a press release announcing Idaho Scientific selected our eFPGA Hard IP for forward-leaning hardware-based cryptographic solutions designed to address mobile, IoT, infrastructure and defense systems.

Idaho Scientific has a rich history in leveraging FPGA technology to deliver robust security systems that can adapt quickly to changing external threats without the vulnerabilities that are inherent in software-based solutions. By integrating our eFPGA Hard IP into its secure System on Chip processors, it can further enhance its cryptographic security and address new markets much more quickly and with lower risks and lower costs. Last April, we announced an eFPGA Hard IP contract with a new defense industrial-based customer valued at $1.1 million that will be fabricated on the GF 12LP process. This application utilizes a large block of our eFPGA Hard IP for critical functions, which is a trend we are seeing in designs targeting advanced fabrication nodes.

With the cooperation of this DIB and its end customer, we are leveraging the large eFPGA core into a new 7-figure contract that we expect to announce this year. However, due to the fact this contract involves multiple parties, it is taking longer than we expected to finalize. Based on current forecast, we anticipate the contract award later this quarter. In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation kit. The evaluation kit, which is currently scheduled for late 2026, will be compatible with common third-party development environments used by both DIBs and commercial customers. This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the discrete FPGA or our eFPGA Hard IP in an ASIC.

In parallel with these efforts, we’re exploring the potential to leverage the FPGA as a chiplet that is co-packaged with one of our partners’ microcontrollers. We are already seeing interest from some of our partners on this concept. We completed the initial phase of our digital proof-of-concept chiplet program in 2025 as a strategy to accelerate our storefront chiplet initiative. Internally, we refer to this as POC. With the support of our large strategic partners, we leveraged our existing eFPGA Hard IP and readily available third-party IP to move this program forward rapidly and with minimal investment. With ongoing debates regarding the communications and protocol layers of chiplet interfaces, this POC and our decades of experience in FPGA bridging positions us well as a potential solution to move chiplet designs forward to satisfy what appears to be significant pent-up demand.

We were invited to present a paper on our POC at the recent Chiplet Summit and at the Intel Foundry’s partners’ presentation at the upcoming GOMAC together with Cadence and Trusted Semiconductor solutions. The net takeaway from our presentation at the Chiplet Summit supports our optimism that chiplets will build traction in 2026. The primary hurdles today are interoperability gaps, and we believe a storefront FPGA chiplet is the logical solution for a programmable bridge. Earlier this year, Epson gave us permission to share its case study that supports our claims that using FPGA technology to process algorithms lowers power consumption without sacrificing programmability relative to processing and software. We published the results in a blog post on January 13.

Epson’s SoC was originally architected to run workloads entirely in software. But as demand for more features and real-time responsiveness grew, power consumption became a limiting factor. Epson’s engineering team recognized that moving compute-intensive functions into dedicated hardware could deliver significant efficiency gains, but the hardware solution would need to be capable of adapting to changes in algorithms. This meant the only practical solution would be an eFPGA core integrated inside the SoC. By using our proprietary Australis eFPGA IP Generator, we were able to quickly deliver a customized Hard IP core specifically designed to the SoC application that targeted TSMC’s e12n fabrication technology. Adding to our challenge was the fact that this would be our first eFPGA Hard IP for e12n.

From design handoff to silicon validation, the IP integrated cleanly into Epson’s SoC without the need for re-spins or late-stage design changes. Epson was able to boot, configure and validate the eFPGA subsystem immediately, accelerating its schedule and reducing risk. After final testing, Epson confirmed the resulting design, reduced overall power consumption by 50%. This makes a huge difference for battery-powered systems. Given our success in this design, we believe we are very well positioned for future opportunities with Epson as well as other companies with similar requirements. As I’m sure you noticed in our 8-K, we took a large impairment charge on SensiML. This is due to the standard accounting practice to impair the value of an asset held for sale for a year or longer.

During the last year, we have discussed the divestiture of SensiML with microcontroller companies. And in one case, those discussions advanced to due diligence, but were concluded without an agreement. We are in discussions today with a large company where SensiML software potentially presents high value for new AI and drone projects. We cannot provide assurance that this or other discussions will result in a transaction. With that, I will turn the call over to Elias for his presentation of financial data.

Elias Nader: Thank you, Brian, and good afternoon, everyone. Total fourth quarter revenue was $3.7 million. This was down 35% from Q4 2024 and up 84% from Q3 2025. New product revenue in Q4 was $2.8 million and mature product revenue was $0.9 million. New product revenue was down 39% from Q4 2024 and up 199% compared to Q3 2025. Mature product revenue was down from $1 million in the fourth quarter of 2024 and $1.1 million in the third quarter of 2025. Non-GAAP gross margin in Q4 was 20.8%. The primary reasons the non-GAAP gross profit margin was below my outlook are $473,000 in inventory reserves and $135,000 in contracted professional services costs attributable to COGS that were not anticipated at the time of our last conference call.

The balance is mostly attributable to a higher-than-expected contribution from professional services relative to IP and mature product revenue. Non-GAAP operating expenses in Q4 were approximately $3.5 million. This was $500,000 above the midpoint of our outlook due to the booking of certain executive incentives in Q4. This compares with non-GAAP operating expenses of $2.9 million in the fourth quarter of 2024 and $2.9 million in the third quarter of 2025. Non-GAAP net loss was $2.9 million or $0.17 per share. This compares to a non-GAAP net income of $0.6 million or $0.04 per diluted share in Q4 2024 and a non-GAAP net loss of $3.2 million or $0.19 per share in the third quarter of fiscal 2025. The difference between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses and the noncash impairment charge for SensiML that Brian mentioned.

Stock-based compensation for Q4 was $700,000 compared to $900,000 in Q4 2024 and $800,000 in Q3 2025. For the fourth quarter, 3 customers accounted for 10% or more of total revenue. At the close of Q4, total cash was $18.8 million, inclusive of $15 million from our credit facility. This compares with $17.3 million, inclusive of $15 million from our credit facility at the close of Q3 2025. This increase of $1.5 million in net cash is inclusive of $3.2 million raised with our ATM during Q4. Now moving to our guidance and outlook for our fiscal first quarter, which will end on March 29, 2026. Based on backlog and customer forecast, our total revenue guidance for Q1 is $5.5 million, plus or minus 10%. We expect total revenue to be comprised of $4.5 million in new product revenue and $1 million in mature product revenue.

For the full year, we anticipate mature product revenue will be approximately $4 million. Based on the anticipated Q1 revenue mix, non-GAAP gross margin for the first quarter is expected to be approximately 45%, plus or minus 5%. For the full year 2026, we are modeling a 57% non-GAAP gross profit margin. However, there are several factors that we believe will weigh on our non-GAAP gross profit margin during the first half of 2026. We are modeling services revenue will be a high percentage of total revenue during the first half. In support of services, we will have costs for software tools that we lease, and we will utilize outside engineering services in addition to our internal resources. A large percentage of these costs are currently being modeled as COGS.

We expect some percentage of these costs will be capitalized, but it is unclear at this point the exact percentage. Also during the first half, we will incur certain significant costs associated with large contracts that will be recognized late during the quarter and the offsetting revenue will not be recognized until the following quarter. We’re modeling these factors as negatively impacting our non-GAAP gross profit margin during Q1 and Q2. Among the significant costs we are modeling for fiscal 2026 are 3 multi-project wafer or MPW tape-outs. All 3 tape-outs are for products that we intend to sell via our storefront program. The costs associated with 2 of these tape-outs will be fully covered by customer contracts. One of these contracts is already on the books and another is in the very late stages of negotiation.

We believe the costs associated with the third tape-out will be covered at least in part by contracts. If contracts are secured in advance of this tape-out, it would be an upside to our full year model. Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs. These classifications are related to labor and tooling for IP products — IP contracts, pardon me. This may cause variability in our quarterly gross margins and operating results that will usually balance out on the operating line. With that in mind, our Q1 non-GAAP operating expense is expected to be approximately $3.2 million, plus or minus 5%. We are expecting full year non-GAAP operating expenses to be approximately $13.5 million.

This forecasted growth of 14% in non-GAAP OpEx over 2025 is to support our anticipated revenue growth in 2026. After interest and other income, we are forecasting a Q1 net loss of about $800,000 or a loss of approximately $0.04 per share. The main difference between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses. In Q1, we expect this compensation will be approximately $800,000, which is similar to Q4 2025 and Q1 2025. As a reminder, there will be movements in our stock-based compensation during the year, and it may vary quarter-to-quarter based on the timing of grants. Prior to this conference call, we raised approximately $3.2 million during Q1 using our existing ATM. We anticipate Q1 cash use net of money raised with our ATM will be approximately $1.4 million.

Our projected Q1 cash use is negatively impacted by the expected timing of payments attributable to our prime U.S. government contract. The timing of these payments during the year are expected to benefit cash flow during the second half. As a heads up, we are working to secure a new banking partner as we are focused on obtaining more favorable terms that will lower our costs and purposely reduce our line of credit from $20 million to $10 million. Thank you for your time. And with that, I will now turn the call over to Brian for his closing comments.

Brian C. Faith: Thank you, Elias. Through hard work, dedication and long hours, the QuickLogic team accomplished numerous strategic milestones in 2025 that has enabled us to enter 2026 on extremely sound footing. Thank you all for what you have accomplished. Our continued performance on our prime U.S. government contract has led to its expansion to a potential $89 million. The addition of GlobalFoundries and its 12LP fabrication process, which is used today by numerous DIBs for a variety of radiation hardness requirements and most recently, the award of a $13 million tranche. Independent of this contract, QuickLogic funded its own strategic radiation hard or SRH discrete FPGA test chip. We now have test chips in hand as well as orders for our SRH FPGA dev kit that will enable DIBs to evaluate our test chip for the full spectrum radiation hardness requirements.

This significantly accelerates our ability to win both discrete SRH FPGA designs we can storefront as well as designs that are better suited to embed our SRH eFPGA Hard IP in ASICs. To further accelerate our storefront business model in 2026, we are planning 3 multi-project wafer or MPW tape-outs this year. All 3 tape-outs are for chips that we intend to sell via our storefront program. The cost for 2 of these tape-outs will be fully covered by customer contracts. One of these contracts is already on the books and another is in the very late stages of negotiation. We believe the third tape-out will be covered at least in part by contracts. Through a revenue-generating contract with a customer, we developed architectural enhancements for our core eFPGA technology that enables us to address the lucrative markets for very high density in both discrete and embedded designs.

These enhancements were initially developed for Intel 18A and are extensible to all advanced fabrication nodes. Given the sound foundation of the recently awarded U.S. government contract, our outlook for continuing mature business of approximately $4 million in 2026 and the number of pending contracts that are in the late stages of negotiation, we believe we are well positioned to deliver between 50% and 100% revenue growth in 2026. With that, I will turn the call over for questions.

Q&A Session

Operator: [Operator Instructions] Our first question is from Richard Shannon with Craig-Hallum Capital Group.

Richard Shannon: Brian, you kind of saved the best for last year with the outlook for the year here. So I guess I’ll start with that topic here and ask for a little bit of help in trying to think about the dollar growth here contributions as we go from ’25 to ’26 in that 50% to 100% here. I wonder if you could tray that by SFR contribution, defense versus commercial and any other ways you’d like to split that up, please?

Brian C. Faith: Sure. So as I said, $4 million of that is going to be our base mature business, which we’re very comfortable with at this point for the year. And then, of course, the $13 million tranche for the U.S. government contract, so that’s $17 million. If you were to look at the range of 50% to 100%, obviously, we need to get well into the 20s to get to that. And we’re expecting that there will be additional contracts that are defense related for either the one of those MPW test ships that I alluded to and/or IP that would be to defense contractors for use in their ASICs. As I mentioned, as we’ve gone and upgraded our architecture to support higher LUT counts, we’re seeing a lot of interest in that type of architecture for some of these process technologies that are tried and true for U.S. defense companies like 18A and 12LP.

And then if you go on top of that a little bit further, we see other commercial IP opportunities, one of which I mentioned during the call that we felt was pushed into 2026 from 2025 with that commercial customer specifically because they were looking at making the IP core larger to handle more capability. And so there was a lot of architectural discussions and trade-offs going on that sort of naturally pushed that IP contract into what we’re now forecasting to be 2026. But that would be a nondefense customer for that particular IP license. Does that give color to the question, Richard?

Richard Shannon: Yes, it does here. So maybe — I probably should have asked this as a multiple-part question here, but maybe I just want to get a little sense of what are the differences between the high and low end of that range here. I think I heard part of it, but I’d love to hear you put that all together, please.

Brian C. Faith: Sure. So the — if you look at the low end of that range, that would definitely be the base $4 million business, the current tranche that we have for the government contract and I’d say a couple of IP licenses, one of which would be useful for one of these MPW tape-outs. And then the higher end or even exceeding the higher end of that would be as we layer additional IP licenses on top of that and perhaps even further funding on the government contract.

Richard Shannon: Okay. That is helpful. Maybe a couple of other questions for me here. So big picture, when we look at strategic rad-hard, both — I asked this question both as FPGAs as well as the opportunity to storefronts for ASICs to include your IP here. What do we think — or how do we think about timing of wins with any of these DIBs for, I think, substantial programs that I think was the intention of this program all along here. Help us understand what you’re expecting to happen this year versus in the following years.

Brian C. Faith: So this year, we’re expecting evaluations to take place using our test chips, either ours or the government-funded one and then getting to some sort of architecture understanding with these DIBs by the end of this year, this fiscal year, next year, starting actual development activity with those chips. So to be clear, this year is very much an evaluation year. All of these companies are very risk-averse from a technical perspective. And so they need the time to dig into the test chip and make sure that they understand it and are comfortable with the tools that go along with it, meaning our software tools and the device and the dev kits themselves. So meaning exiting this year with their positive feedback and sort of thumbs up that they want to move forward with architecture insertion next year.

Richard Shannon: Okay. That is helpful perspective. Maybe jumping back quickly to the thought process for the year here. You mentioned a sales number and then Elias also gave us some other numbers. I wasn’t able to put those together here to understand whether we’re going to be net income positive or cash flow positive this year. Maybe you can help us understand your thought process either both at the low and the high end of your sales guidance range.

Elias Nader: Well, I’ll tell you if it’s — we’re expecting cash flow positive on the second half of the year for sure, not the first half, Richard.

Richard Shannon: Okay. And how about net income or EPS? What’s that looking like on the bottom line?

Elias Nader: Same. I think we’ll be on the high end in the second half of the year and not the first half as well. But I expect to be both positive on net income in the second half of the year.

Richard Shannon: Okay. That is helpful. And one last question for me, and I’ll jump out of the line here. Brian, you mentioned targeting 3 MPWs this year. And I think I’ve lost a couple or some of the details you offered regarding that. But maybe you can help us understand the dynamics here? And is this something that’s kind of follow-on to the ones you got on last year? Or are these blossoming opportunities that you expect to continue to do here? Like how should we think about these? And I can’t remember also, did you mention the process node or even foundries that those would be on.

Brian C. Faith: Yes. We did not mention process technology for these, and I’m not going to. But they are based on process technologies that we already support. So we don’t have to do an actual physical port to a new process to execute on these. And I think we’re trying to convey that 2 of these will be fully covered by customer contracts and one of them would be partially covered by the contract. The key here being that there’s going to be end customers associated with all 3 of them. They are the driving force behind the definition of these. And in some cases, like we mentioned, either partial or fully funding the development of them during the year.

Operator: Our next question is from Neil Young with Needham & Company.

Neil Young: The first question, I wanted to ask about the high-performance data center win that you talked about in the press release. Maybe if you could dig a little bit deeper on that, share what the application is? Just any other color, I think, would be interesting.

Brian C. Faith: Sure. So this is a 12-nanometer design, and it’s for an eFPGA IP core. The eFPGA IP core for this particular one is a meaningful percent of the die size, meaning it’s not just an insurance policy, it’s actually delivering capability that they’ve architected in from day 1 to be very important for the functionality of this chip. Because it’s not a 3- or 4-nanometer chip, obviously, it’s not going to be a GPU class device. But there’s a lot of peripheral components in these data center printed circuit boards that surround those types of devices. And this would be an example of one of those, let’s call it, peripheral chips that are still important and critical for overall functionality, but not at the core of the compute.

So we’re continuing to execute on that, continuing our engagement with the customer and hopefully supporting their tape-out at some point later this year. The nice thing about it — I’m glad you brought it up, Neil, because this is sort of the — probably the largest IP contract we’ve had in recent times for a nondefense application. And a lot of people have asked us repeatedly, are you going to be beyond just defense? And we said, yes. And I think it’s glad that we’re able to talk about this particular example because it clearly is a nondefense application, and we believe hopefully the start of other nondefense applications as well. The other one I’ll mention is Epson, right? We gave Epson more airtime today in the call based on that blog.

That’s also an example of a nondefense use. So it’s been a while getting to more commercial customers, but I think we’re starting to see a little bit more momentum and interest there now that we have these other process technologies supported.

Neil Young: That makes sense. The other question I had, I’m just interested in the competitive dynamics. So you talked about the potential storefront business being pretty large for this discrete strategic rad-hard FPGA during the coming year and the year after that. I was curious if the competition differs at all from your traditional eFPGA IP that you’ve talked about. So just anything different on the competition front would be helpful, just understanding that.

Brian C. Faith: Sure. So if we go up to 50,000 feet and we say, what’s the programmable logic umbrella in total, there’s eFPGA and there’s FPGAs. And most people know the FPGA competitors, or I guess, the peers, if you will, some of them not really competitors, would be Xilinx and Altera and the FPGA division of Microchip and Lattice and Efinix and Achronix. Those are sort of the companies that do discrete FPGA devices. Now of those, if we think about what are the ones that are U.S.-based and have a defense focus and [ 2 ] devices that would fall into this category of some level of radiation hardness, you can kind of go and zoom in and say, okay, well, today, Microchip has devices from their Actel acquisition long ago that do this rad-tolerant, to some extent, rad-hard.

Xilinx has some rad-tolerant, I think 1 rad-hard device. I think Altera has some, although I admit I haven’t looked at their product portfolio recently. And I think Lattice would like to get into defense and doesn’t really have anything today in that area. I don’t think Achronix has. I think Efinix is mostly focused on Asia. So you already whittle down pretty closely to just a couple of people that do any level of serious radiation hardness or tolerance. But when you compare and you say, okay, well, let me move the bar and say, it has to be manufactured onshore and it’s got to meet strategic levels. I would challenge anybody to go to the websites of those companies I just mentioned and point to a device that meets those requirements. I think it’s an all set.

So I think we’re really well positioned in that sense as we continue to execute on this program. Now the other part of the programmable logic umbrella, as I mentioned, is eFPGA IP. And none of those companies that I just mentioned have a real eFPGA IP business. They want to sell new devices because they view IP as undermining device sales, I would imagine. From an IP perspective, there’s really just a couple of companies that have done IP in the last few years besides QuickLogic. One is called Flex Logix that was acquired last year by Analog Devices and made captive, so they don’t do licensing anymore. And now there is a French start-up company called Menta and they have licensable IP. And then there’s a couple of really tiny academically oriented companies that I won’t even give airtime to today.

So if you compare us against one company, Menta, again, I go back to we’re a more established company. We’re doing business with all these big companies. We have the spectrum of IP2 devices. We’re a U.S. company, products made in the U.S. So we have a lot of, I would say, differentiation at that level compared to Menta. But the more important one is when you dig into the technical details, Menta is a soft IP company. And so soft IP means that when you’re licensing IP to a customer, they’re not just getting soft IP, they’re getting a big boatload of work to make it a hard IP before they put it into their ASIC. And with that boatload of work comes a lot of risk and time and cost. And when you’re a hard IP supplier like we are, we take care of all that.

They don’t have to worry about designing anything. They just need to think about how do I architect and use this IP. And so there’s a huge difference in the engagement model between us and Menta. And that’s, I think, reflected in the wins that we’re announcing, who is using us. It’s also reflected in the average selling price of our IP, right? We’re not doing soft IP that is a $20,000 IP that comes with it a lot of work. You’re licensing something for quite a bit more money, but we’re taking care of that work and risk for the customer. And that’s the huge difference between us and Menta as far as the eFPGA IP goes. Hopefully, that helps as an update on the competitive [ metrics ].

Operator: Our next question is from Tyler Burmeister with Lake Street Capital Markets.

Tyler Burmeister: So first, great to see the next tranche of the U.S. SRH development program, the $13 million you got as well as the announcement that the program had expanded with GlobalFoundries process. Maybe it’s a little bit of a follow-on from an earlier question. I think you said potentially in the high end of expectations this year, you could see more funding. But to the extent you’re able to, I’m just wondering, could you give any color on what next milestones we should be expecting or looking forward to from that program?

Brian C. Faith: Sure. I’m asked this question a lot, Tyler. And unfortunately, I can’t give programmatic details out on the program. But what I can say is I’ll go back to something I was given permission to say when we first got this contract in 2022, which is that the scope of this whole contract contemplates 2 devices, a test chip and a final chip. And so we were able to say, I think it was in December press release when we announced the contract ceiling expansion to $89 million and adding GlobalFoundries that we had, in fact, taped out a test chip for that contract. So you can sort of check one off the list there of the 2. So you can imagine I think it’s a natural extension that with more funding, especially the rate — the increase in the funding from this year over last year and the fact we’ve already done 1 but not 2 chips that we’re embarking on that second chip development now.

And unfortunately, I’m not going to be able to give really specific details on what’s in the chip and when we’re taping it out and when it’s going to come out, but it’s all in line with our obligations to the government for this contract.

Tyler Burmeister: Yes. That’s perfect. I appreciate the extra color there. And then the full year guidance was great, and I appreciate the details around that. Just putting the pieces together, strong Q1 and a number of initiatives kind of coming together at the same time here. Would it be reasonable to potentially expect some lumpiness through the year, maybe Q2 sequentially down? Or do you think you could grow revenue sequentially kind of linearly through the year?

Brian C. Faith: So we actually think that Q1 is going to be the low point for the year, right? We’ll give that breadcrumb, that the other quarters will be over Q1. There may be some lumpiness. And the reason why I say maybe is that when you’re dealing with contracts that are $2 million, $3 million each, especially if it’s IP and it’s recognized on delivery, then there’s some natural lumpiness to when we get the contract and we make the delivery in a particular quarter, right? So there may be lumpiness from that perspective. But I think we’re trying to give this outlook that Q1 is actually the low point for the year, that it’s going to be up from here.

Operator: Our next question is from Gus Richard with Northland Capital Markets.

Auguste Richard: Just on Q3, you guys mentioned a $3 million commercial contract that you expected the revenue in Q4, didn’t look like you did. Is that part of the guide for Q1?

Brian C. Faith: No, it’s not. In this call, we said that we’re expecting or forecasting that to be contracted in Q2. And so that $3 million is not part of the Q1 guide. The other thing I’ll add, Gus, is when we said initially Q3 and then in Q4, we said it may be in there or not, and it clearly got pushed. This is the one where we had said that now what they’re looking at is a larger eFPGA core. And because they’re looking at larger cores, they want to basically take more time on the technical feasibility side and diligence before we execute a contract. But it’s not in the Q1 guide to be very clear.

Auguste Richard: Okay. And that contract is upside if I heard you correctly.

Brian C. Faith: I’m sorry, could you…

Auguste Richard: The value of the contract was increased.

Brian C. Faith: Yes. Well, we said the size of the core has increased. We didn’t say the value of it has increased, but the amount of eFPGA logic that they want is definitely larger than what they had originally thought of.

Auguste Richard: I understand. And then my next question is for the test chip that you guys taped out and have gotten samples back and you’re getting orders for the test development boards. When do you expect those to start to ship? And how much revenue do you think you can generate and from how many customers?

Brian C. Faith: Several questions in there. Let me unpack that. So — and for clarity, we’ve talked about 2 test chip tape-outs now, right, publicly. We’ve talked about the government-funded one. We’ve talked about the self-funded one. So because I can’t give updates on the government one by my obligations to the government, I can just talk about our self-funded one. So on the self-funded one, we did receive the chips in Q1. I’d say the fab was a little bit later than what we had planned on for that. Our engineering team is working on those chips right now and going through the validation process. And what I’ve said previously is that as soon as we have those validated, then we’ll make sure that we can get those out to fulfill the test chip for the dev kit orders.

And I think we’ve said previously, we’d love to get it out by the end of Q1. If it’s into Q2, then that’s fine, too, because we intentionally did this test chip tape-out. So we gave ourselves a lot of buffer in terms of time for us to get these into the hands of the DIB for them to do the evaluations that they need to do to get comfortable. And I think your last question, Gus, there was how many customers. So the nature of this type of device being rad-hard means that there aren’t a lot of people that you’re actually allowed to sell it to, clearly U.S.-based. And the nature of this is really for the strategic defense systems, and there’s only a handful of those that actually design for any kind of subsystem in those devices or systems, I should say.

So our target is less than 5 because those 5 really, really matter in terms of these major systems.

Auguste Richard: Got it. And then my last one is on gross margins. How do we think about the trajectory of gross margins going through the year? Non-GAAP 45% for the first quarter, does that step up at all in the second quarter and — or is it more of a linear ramp? How do we think about that?

Elias Nader: Q1, we said 45%, give or take. Q2 would most likely be around the same flattish. And Q3 and Q4, I see an upside big time on gross margins. I have to say, over the time I’ve been here, this has been the most difficult piece of the puzzle to gauge and forecast, mainly because of the way we capitalize certain COGS and move certain things into OpEx and otherwise. So it’s been a very tough exercise to do, but we’re getting there. But overall, I see a decent 57% for the full year in terms of gross margin that I said in the script.

Operator: Our next question is from Rick Neaton with Rivershore Investment Research.

Richard Neaton: I just had one question about chiplets. And you’re talking about your bridging technology that you’ve used in the past with programmable logic. How do you see these chiplet applications using programmable logic in what end uses are some of these being contemplated? And when you say — the second part of the question is on bridging, are you talking about bridging on the chiplet or between chiplets?

Brian C. Faith: Okay. So 2 questions there. One is really the use case, the end applications for chiplets? And then one is, I guess, how are they partitioned within these packages? Is it all resident in one chiplet? Or is it multiple chiplets to solve the problem, right?

Richard Neaton: Right, right. Are you bridging between layers on a chiplet or are you bridging between multilayer chiplets? I’m just curious.

Brian C. Faith: I think — yes. No, I can elaborate on some of this. So on the — let’s start with the end markets and use cases for the chiplets. So I think we’ve talked about this before, but aerospace and defense is a really big market for chiplets because they don’t want to have to do a bunch of custom ASICs if they can avoid it because their volumes are not terribly large, and it costs a lot of money to go off and do these custom ASICs. So to the extent they can make things heterogeneous inside the package, it’s going to really help offset their program costs for development. So eFPGA in that case, you can almost look at where are FPGAs used today in those systems and that becoming a chiplet and connecting them with other devices that FPGAs interface with in those systems today.

So in those systems today, you generally have some sort of big processor, could be a flight computer. The FPGA technology today is very useful for signals that are coming in from sensors, doing preprocessing on those signals and packetizing them in a way that the actual CPU or SoC can process on without having to redo a lot of that capability that the FPGA is doing. Because remember, FPGAs are very good at real-time, highly parallelized computation. So that’s sort of the overall defense use case for these. And again, you can imagine that there’s a lot of software that’s already been written in the defense industry for certain processor architectures, there’s already a lot of FPGAs used. Packaging those die or capabilities inside one package actually saves on the A and PPA, which is area, right?

A lot of these systems are going for more miniaturization and they’re looking at packaging these things in a single package to do that. So that’s the big use case there. I’d say outside of defense, there’s a lot of interest for security or things that are sort of protected from this post-quantum era of computing for really just protecting systems from a cyber perspective. And eFPGA or FPGA is good for that because in the event that anything is hacked in the future, if the hardware itself is programmable, then you can reprogram whatever algorithm that you have in those to adapt to that threat at the time. And so there’s interest in that as far as making these systems more trusted. And I don’t mean trusted from a defense perspective, I mean trusted in the sense that you can trust that it’s running what it’s supposed to be running and nothing more than that.

So that’s also an interesting use case that’s coming up for eFPGA chiplets. Again, the same idea being they’ve got a lot of software and infrastructure already. How can they adapt that existing infrastructure by adding a little bit of programmability and not redesigning all the ASICs. So that’s a good use for an eFPGA chiplet. Now as far as the bridging goes, you can see from these examples that we’re not replacing the whole SoC with this eFPGA. It’s basically taking the capability of a discrete FPGA and getting it inside the same package as what the SoC is or the ASIC is in their system architecture. And then as far as the actual bridging goes, chiplets is kind of like if you go back to when USB or PCI was first being broadly adopted in the PC or laptop era of growth, that sort of happened.

That was successful because everybody was able to standardize on a common interface, right? PCI is PCI, USB is USB. You design a peripheral with that, you go to the plug fest, everything works, everybody is happy. In chiplets, it’s a lot more complicated than that because you have these different flavors of UCIe as an example, and you have a bunch of wires, BOW, and they’re incompatible. And so there isn’t this notion of like universal compatibility. And then if you dig even further into the details, if you want to, there’s a difference between the physical layer and the protocol layer, right? So you can imagine like a physical layer is me writing a note on a piece of paper and passing it to you, right? I pass the paper, you receive it, we’re all good.

But if I’m writing in a different language than what you understand, it’s going to look like gibberish when you try to read that paper. And the same thing is happening with UCIe, where the physical layers may be compatible, right? UCIe cores on both sides, but the protocol that people are putting over UCIe are different. And that’s exacerbated by people doing ASICs at different points in time. So one of the things with our eFPGA is we’re thinking, well, that hardware is actually programmable. So as long as the physical layers are connecting and as long as you have enough gates in our FPGA, you can probably program them to add some level of compatibility or in my paper analogy like a translator. And so we’re hopeful that some of those will actually come to fruition based on that value proposition.

And we’re starting to get some positive feedback on that idea based on what we heard at the Chiplet Summit last week, and I think what we’re going to hear at GOMAC next week in Louisiana when we’re there presenting. Does that help the use cases?

Richard Neaton: Yes. No, I appreciate the color.

Operator: Our final question is a follow-up from Richard Shannon with Craig-Hallum Capital Group.

Richard Shannon: Just one last question for me. Brian, again, hitting on the topic of strategic rad-hard and actually probably want to extend this maybe to rad-hard given your comments on the call today here. But how many distinct programs are you bidding on here? I know you’re not going to tell us an exact number, but I was hoping you could use language like a couple of few, several over a dozen, that sort of thing here. Just help us get a sense of the number of programs you’re bidding on.

Brian C. Faith: I would say the immediate ones that are the highest level of radiation hardness, there are less than 5 major programs, but there are several subsystems within each major program that we would like to be inserted into. So I guess you could — what you hear about there is the total number of socket opportunities in that kind of part of land. And that would be I don’t know, 10 to 20 total. And that’s for the highest level of radiation, which has been our focus because that’s the greatest area of differentiation. If you start relaxing the radiation hardness requirements, obviously, you can get into a lot of new applications around space. And there’s going to be tens of applications in space. But the initial focus, especially for these first dev kit orders is going to be the ones that are the higher levels of radiation where we don’t have a competition at this point.

Richard Shannon: That’s great perspective, Brian.

Operator: There are no further questions. I would like to turn the conference back over to Brian Faith for closing remarks.

Brian C. Faith: Thank you. And we will provide a technical presentation on our chiplet POC at the Intel Foundry’s partners’ presentation at the upcoming GOMAC, March 10, together with Cadence and Trusted Semiconductor Solutions. In April, we will exhibit at HEART, which is another government radiation effects-oriented conference and also exhibit and present at IP SoC Days in Silicon Valley, again, in April. Thank you for your support and for joining us today, and we’ll talk with you next time. Thank you. Goodbye.

Operator: Thank you. This will conclude today’s conference. You may disconnect at this time, and thank you for your participation.